The microelectronics industry is in constant pursuit of increasing the speed and performance of microprocessors. Complementary metal-oxide semiconductors (CMOS), the major class of integrated circuits used in microelectronics, are a particular area of interest. High-carrier-mobility CMOS devices are being investigated because of their potential for enhancing electron (n-type) and hole (p-type) mobility. In order to fully realize the potential of high-carrier-mobility CMOS devices, the development of new materials that are compatible with the scaling of device dimensions is required.
It is well established that strain modifies the band structure of Si, thereby influencing the charge carrier mobility (Schäffler, F., Semicond. Sci. and Technol. 12, 1515 (1997)), among other effects. Tensile strain in Si(001) produces significant electron mobility enhancement, but degrades the hole mobility at low levels of strain (Rim, K., et al., IEDM Tech. Digest 3.1.1. (2003)). Advanced CMOS applications demand both high electron and high hole mobility. To achieve that goal with Si(001) alone would require the use of very highly strained Si(001), a difficult condition to achieve.
For high-mobility p-type devices, Si(110) is an attractive alternative; as its hole mobility is about twice that of Si(001), although it is still much lower than the Si(001) electron mobility (Sato, T., Takeishi, Y., and Hara, H., Phys. Rev. B 4, 1950 (1971). However, when a (110) oriented Si lattice is under biaxial tensile strain, the hole mobility is dramatically enhanced even for relatively small values of strain, and the electron mobility can be improved to a value in excess of 80% of the electron mobility found in unstrained Si(001) (Mizuno, T., Sugiyama, N., Tezuka, T., Moriyama, Y., Nakaharai, S., and Takagi, S., IEEE Trans. Electron Devices 52, 367 (2005)). Consequently, strained Si(110) is a good candidate for both high-speed pMOS and advanced CMOS applications where reducing the current drive imbalance between n-type and p-type channels is a major concern. There is also considerable interest in using non-traditional crystal orientations to optimize carrier mobility, by fabricating mixed regions of Si(110) and Si(001) on a single wafer (so-called hybrid-orientation technology (HOT)). HOT architecture allows fabrication of p-channel devices on the high-hole-mobility Si(110) regions, and n-channel devices on the high-electron-mobility Si(100) regions (Yang, M., et al., IEEE Trans. Electron Devices 53, 965 (2006)).